
SECTION 2 HARDWARE DESCRIPTION
15
and provides enhanced data recovery margins in both single and
double density. The loop is constructed of both digital and
analog circuitry.
Figure 2-14. Phase Detector and Filter
The Voltage Controlled Oscillator (VCO) is a 741S123 with
both sections configured to trigger each other. The control
voltage is applied to the resistors R3 and R4/5. An increase in
voltage corresponds to an increase in frequency. IC 2A, a
section of a 741S123, also uses VX to provide this one-shot with
a period which proportionally tracks the period of the VCO. See
Figures 2-14 and 2-15.
A set of timing signals are generated from the VCO which are
used by the Digital Phase Detector. IC's 1C and 3A are 741S1138
and are used to generate these signals. They are all clocked
simultaneously to eliminated any skew in the generated signals.
In the following discussion 8 inch operation is assumed (With 5
inch operation all timings are doubled). In double density
(MFM), the incoming data stream contains bits which are
separated by 2, 3, or 4 microseconds (wishful thinking!). Read
Clock makes a transition every 1us. The Phase-Locked Loop
adjusts the VCO such that each data pulse is centered in the
middle of a half-cycle of Read Clock (Window). More precisely,
due to bit-shift, very few individual data pu1ses are centered.
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