
SECTION 2 HARDWARE DESCRIPTION
9
BIT FUNCTION SECTION
A3
A4
A5
A6
A7
Issue Step Pulse
Clear Timer
Reset Host Interrupt
Initiate Timer
Wait State Request
2.15
2.14
2.5
2.14
2.16
Table 2-4. Address Bit Assignments
2.12 BOARD LEVEL STATUS PORT
The Board Level Status Port is a parallel input port to the
onboard Z80A. It provides the processor with access to board
signals that cannot be read from the FD 1791-01. These signals
are listed and described in Table 2-5. See Figure 2-7 for
circuit diagram.
DATA
BIT
SINGAL
NAME
DESCRIPTION
0
1
2
3
4
5
6
7
UO
U1
TST*
ZINT
SERI
TOFF
ILP*
CHNG*
User 0 switch setting
User 1 switch setting
Test mode
Interrupt req from host
EIA level input bit
Timer off
Illegal pack inserted
Disk has been changed
Table 2-5. Board Level Status Bits
Figure 2-7. Board Level Ports
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