Qume DataTrak 8 Manual descargar pdf (Pagina 22)

SECTION 2 HARDWARE DESCRIPTION

2.19 MEMORY CONTROL

The Memory Control Circuit is used to operate the on-board

memory. When SLVACK* is high, the on-board Z80A is performing

memory read and write operations. When the internal memory is

present in the 8100 bus (SLVACK* low), the host processor may

perform read and write operations. Refer to Figure 2-12 for

circuit diagram.

Figure 2-12. Memory Control Circuit

S100 bus requests for read and write operations are decoded

by IC 2K. IC 2K pin 6, when high, indicates a memory read is

taking place. IC 1M pin 6 can be used to provide PHANTOM* to

the S100 bus to avoid a bus driver conflict when using memory

cards which overlap the selected memory window address. Many 64k

dynamic RAMs cannot disable 1K segments. IC 1F pin 3 is used to

enable the data out driver, IC 4J. R13 and C15 provide

approximately 120 ns. turn-on delay, allowing PHANTOM* enough

time to turn any other memory off. IC 2K pin 8 indicates a bus

write is about to take place. This signal pulls IWR* down

indicating to the 2114's that this is a write cycle. MDI* is

also asserted, which enables the data-in buffer (IC 4K). When

pWR* is asserted IC 4A pin 11 goes high. Either pin 6 or 8 of IC

1K then enables _ bank of 2114. The memory bank selected is

determined by IA10 and IA10* applied to pins 3 and 11 of IC 1K.

IC 3C detects the on-board processor read cycle. IC 1K again

provides the bank enable signal. An on-board processor write

cycle is detected by one-shot OL (IWR* and IMREQ*). The output

OL pin 13 is used to strobe the appropriate bank enable (through

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 ... 46 47

Sin comentarios

Qume DataTrak 8 Manual Pagina 22