Qume DataTrak 8 Manual descargar pdf (Pagina 21)

SECTION 2 HARDWARE DESCRIPTION

2.16 WAIT STATE GENERATOR

The Wait State Generator is

used to synchronize the on-board

processor to the Disk Controller

when data is being transferred

between the Double-D and la disk

drive. The wait state is

generated during the execution

of an input instruction from the

Board Level Status Port while

address bit A7 is held high. The

wait-state is held until the FD

1791-01 issues either a Data

Request (DDRQ) or an interrupt

(DINT). For circuit details

refer to figure 2-10.

Figure 2-10. Wait States

2.17 VECTOR INTERRUPT GENERATOR

The Vector Interrupt Generator may optionally be used to

issue an interrupt to the host processor system. The interrupt

is issued on one of VIO* thru

VI7*, selectable by jumper, when

the on-board processor executes

the HALT instruction. The

interrupt request is terminated

when the host processor either

switches the Double-D memory

into the S100 bus or issues an

interrupt to the Double-D. See

figure 2-11 for circuit details.

Figure 2-11.

Vector Interrupts

2.18 EIA LEVEL INTERFACE

The EIA LEVEL INTERFACE provides the level conversions to and

from TTL. These EIA level lines are made available at connector

J4, an 8-pin DIP socket located close to IC 1A.

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Qume DataTrak 8 Manual Pagina 21