Qume DataTrak 8 Manual descargar pdf (Pagina 23)

SECTION 2 HARDWARE DESCRIPTION

IC 1K). During this strobe IWR* is held low,' indicating a write

cycle for the 2114s.

2.20 WRITE PRECOMPENSATION

The Write Precompensation circuit is used advance or retard

the individual write data pulses. This is done to correct for a

distortion called BIT SHIFT. This bit shift .is observed when

reading a data stream from 1:1 diskette. Data pulses which are

recorded close together, when read back, appear to spread apart.

This circuit shifts the pulses being recorded in the direction

opposite of the direction of this bit shift. The 1791-01

provides two signals, EARLY and LATE, which are used to advance

or retard the individual data pulses. See Figure 2-13 for

circuit diagram.

Figure 2-13. Write Precompensation Circuit

Signals PCA and PCB are used to produce three different

voltage levels at U4 pin 5. This level is amplified by U4 and

then used as the pull-up voltage source for one-shot 1A.. R30

and R31 are individually switched by EARLY and LATE to vary the

one-shot period. R28 is always in circuit. It determines the

longest period. When neither EARLY nor LATE are applied, R28

and R31 in parallel determine the period. With EARLY asserted,

R30 is included in parallel to provide the shortest period. The

amount of precompensation applied is the difference between the

normal period and either the short period or the long period. By

selecting the voltage applied to the pull-up resistors, the

amount of precompensation is varied. IC 3B is used to inhibit

precompensation when PCA and PCB are both low.

2.21 PHASE-LOCKED LOOP

A Phased-Locked Loop is used to generate the read clock as

required by the 1791-01 for data separation. This method was

selected as it provides maximum immunity to disk speed variation

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Qume DataTrak 8 Manual Pagina 23